The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 22, 2008
Filed:
May. 25, 2006
Katsumi Tokuyama, Osaka, JP;
Takeshi Hirayama, Osaka, JP;
Katsumi Tokuyama, Osaka, JP;
Takeshi Hirayama, Osaka, JP;
Matsushita Electric Industrial Co., Ltd., Osaka, JP;
Abstract
An integrated circuit device is provided which can increase a stable area having less digital noise. A data delay adjustment circuit group () is fed with data outputted from a flip-flop circuit group (), adjusts a delay of the data so as to synchronize the operation of a data output terminal group () with the operation of a logic circuit (), and outputs the data to the data output terminal group (). A clock delay adjustment circuit () similarly adjusts a delay of a clock outputted from an inverter () and outputs the clock to a clock output terminal (). Therefore, the operations of data output terminals are synchronized with the operation of the logic circuit () while keeping the phase relationship between an external output clock and external output data.