The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 15, 2008
Filed:
Jul. 25, 2002
Mark D. Hayter, Menlo Park, CA (US);
Shailendra S. Desai, San Jose, CA (US);
Daniel W. Dobberpuhl, Menlo Park, CA (US);
Kwong-tak A. Chui, Cupertino, CA (US);
Mark D. Hayter, Menlo Park, CA (US);
Shailendra S. Desai, San Jose, CA (US);
Daniel W. Dobberpuhl, Menlo Park, CA (US);
Kwong-Tak A. Chui, Cupertino, CA (US);
Broadcom Corporation, Irvine, CA (US);
Abstract
A packet processing system may include a processor, a cache, a memory controller, and at least one packet interface circuit integrated into a single integrated circuit. In one embodiment (which may be used in integrated or non-integrated systems), the packet interface circuit is configured to cause allocation in the cache of a portion of a received packet. In one embodiment (which may be used in integrated or non-integrated systems), the memory controller may be configured to selectively block memory transactions. Particularly, the memory controller may implement at least two block signals, one for the packet interface circuit and one for other devices. The block signals may be used to control the initiation of memory transactions when the memory controller's input queue is approaching fullness.