The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 15, 2008
Filed:
Aug. 28, 2003
Michael Harms, Pleasanton, CA (US);
Eric C. Chang, Cupertino, CA (US);
Paul Tracy, Sunnyvale, CA (US);
John Dicosola, Pleasanton, CA (US);
Mandrita Brahmachari, Milpitas, CA (US);
Michael Harms, Pleasanton, CA (US);
Eric C. Chang, Cupertino, CA (US);
Paul Tracy, Sunnyvale, CA (US);
John DiCosola, Pleasanton, CA (US);
Mandrita Brahmachari, Milpitas, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
The present invention is a novel method and computer program product which utilizes an interface capacitor formed by the metal of the probe tip, a dielectric layer, such as an oxide, formed by a contaminant on a solder bump and the metal of the solder bump. The interface capacitor forms a capacitive divider with the inherent capacitances of the automatic test equipment and the device under test (DUT). The voltage characteristics of the capacitive divider are used to drive voltage signals across the interface capacitor to test the DUT. In either direction (i.e. from the automatic test equipment to the DUT or vice versa), by altering the voltage output high amplitude of the driver and/or the voltage input high amplitude of the load, the DUT is validly tested through the interface capacitor. Thus, even if all I/O bumps have an oxide layer, the device may still be validly tested.