The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 15, 2008
Filed:
Mar. 16, 2001
Stefan Bader, Eilsbrunn, DE;
Berthold Hahn, Heman, DE;
Volker Härle, Laaber, DE;
Hans-jürgen Lugauer, Sinzing, DE;
Manfred Mundbrod-vangerow, Oxenbronn, DE;
Stefan Bader, Eilsbrunn, DE;
Berthold Hahn, Heman, DE;
Volker Härle, Laaber, DE;
Hans-Jürgen Lugauer, Sinzing, DE;
Manfred Mundbrod-Vangerow, Oxenbronn, DE;
Osram GmbH, Munich, DE;
Abstract
An LED chip comprising an electrically conductive and radioparent substrate, in which the epitaxial layer sequence () is provided on substantially the full area of its p-side () with a reflective, bondable p-contact layer (). The substrate () is provided on its main surface () facing away from the epitaxial layer sequence () with a contact metallization () that covers only a portion of said main surface (), and the decoupling of light from the chip () takes place via a bare region of the main surface () of the substrate () and via the chip sides (). A further LED chip has epitaxial layers only. The p-type epitaxial layer () is provided on substantially the full area of the main surface () facing away from the n-conductive epitaxial layer () with a reflective, bondable p-contact layer (), and the n-conductive epitaxial layer () is provided on its main surface facing away from the p-conductive epitaxial layer () with an n-contact layer () that covers only a portion of said main surface (). The decoupling of light from the chip () takes place via the bare region of the main surface () of the n-conductive epitaxial layer () and via the chip sides ().