The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 08, 2008
Filed:
Mar. 11, 2004
Richard Lee Donze, Rochester, MN (US);
William Paul Hovis, Rochester, MN (US);
Terrance Wayne Kueper, Rochester, MN (US);
John Edward Sheets, Ii, Zumbrota, MN (US);
Jon Robert Tetzloff, Rochester, MN (US);
Richard Lee Donze, Rochester, MN (US);
William Paul Hovis, Rochester, MN (US);
Terrance Wayne Kueper, Rochester, MN (US);
John Edward Sheets, II, Zumbrota, MN (US);
Jon Robert Tetzloff, Rochester, MN (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
An apparatus and method is disclosed for improving timing margins of logic paths on a semiconductor chip. Typical logic embodiments, such as CMOS (Complementary Metal Oxide Semiconductor), have path delays that become shorter as supply voltage is increased. Embodiments of the present invention store product data on each particular chip. The product data includes, for examples, but not limited to, a voltage range having a low limit voltage and a high limit voltage, a limit temperature, and performance of the particular chip in storage for the particular chip. Each chip has a voltage controller, a timer, and a thermal monitor. The voltage controller communicates with a voltage regulator and dynamically causes a voltage supply coupled to the chip to be as high as possible in the voltage range, subject to the limit temperature.