The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 08, 2008

Filed:

May. 10, 2005
Applicants:

Shifeng Zhao, Plano, TX (US);

Cetin Kaya, Plano, TX (US);

James Teng, Dallas, TX (US);

Claus Neesgaard, Plano, TX (US);

Lieyi Fang, Plano, TX (US);

Jeff Berwick, Sunnyvale, CA (US);

Inventors:

Shifeng Zhao, Plano, TX (US);

Cetin Kaya, Plano, TX (US);

James Teng, Dallas, TX (US);

Claus Neesgaard, Plano, TX (US);

Lieyi Fang, Plano, TX (US);

Jeff Berwick, Sunnyvale, CA (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03F 3/217 (2006.01);
U.S. Cl.
CPC ...
Abstract

A system and method is provided for detecting an over-current condition in a power field-effect transistor (FET). In one embodiment, an over-current detection circuit for detecting an over-current condition in a power FET comprises a current generator circuit operative to generate a reference current and a plurality of matched FETs operative to receive the reference current and provide a reference voltage, the matched FETs being matched to each other and to the power FET. The over-current detection circuit also comprises a comparator operative to measure a drain-to-source voltage of the power FET and to provide an output that indicates that the drain-to-source voltage of the power FET has exceeded the reference voltage.


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