Voltage translator circuit and semiconductor memory device

Abstract

A voltage translator circuit capable of operating at high speed, saving the power consumption, and forming to have a smaller circuit area. When the output level of a decoderis changed from the potential GND to the potential VDD, a pMOS transistoris turned off, and the gate of nMOS transistorcomes to have a high impedance. Because of this, the self-boost effect acts on the gate of the nMOS transistorto push up the source potential of the nMOS transistor. Consequently, the gate potential of the pMOS transistoris abruptly raised, and this pMOS transistoris turned off at high speed. The pMOS transistorbeing turned off at high speed, the penetration current flowing through the transistorsandis reduced and the electric potential of the word line WL falls at high speed. This voltage translator circuit can be achieved only by adding a low voltage pMOS transistorto the prior art voltage translator circuit, thus enabling the circuit area of the voltage translator circuit to make smaller.