The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 01, 2008
Filed:
May. 17, 2004
Hitoshi Watanabe, Kawasaki, JP;
Hideaki Konishi, Kawasaki, JP;
Yuko Katoh, Kawasaki, JP;
Kazuyuki Yamamura, Kawasaki, JP;
Naoko Karasawa, Kawasaki, JP;
Takeshi Doi, Kawasaki, JP;
Osamu Ōkano, Kawasaki, JP;
Junko Kumagai, Kawasaki, JP;
Koichi Itaya, Kawasaki, JP;
Daisuke Tsukuda, Kawasaki, JP;
Ryuji Shimizu, Kawasaki, JP;
Toshihito Shimizu, Kawasaki, JP;
Hitoshi Watanabe, Kawasaki, JP;
Hideaki Konishi, Kawasaki, JP;
Yuko Katoh, Kawasaki, JP;
Kazuyuki Yamamura, Kawasaki, JP;
Naoko Karasawa, Kawasaki, JP;
Takeshi Doi, Kawasaki, JP;
Osamu Ōkano, Kawasaki, JP;
Junko Kumagai, Kawasaki, JP;
Koichi Itaya, Kawasaki, JP;
Daisuke Tsukuda, Kawasaki, JP;
Ryuji Shimizu, Kawasaki, JP;
Toshihito Shimizu, Kawasaki, JP;
Fujitsu Limited, Kawasaki, JP;
Abstract
A design support apparatus includes a unit that inputs a user net list created by using hard macro cells excluding test circuits, and a unit that arranges hard macro cells using a frame into which hard macro cells, where timing-converged physical information includes test terminals, and test circuits are embedded as arrangement/wiring information. Moreover, includes a unit that arranges and wires the test circuits using the arrangement/wiring information of the test circuit embedded into the frame, a unit that recognizes arrangement/wiring information where the arrangement/wiring information of the test circuits is removed from arrangement/wiring information obtained by wiring, and a unit outputs a net list of a logic structure.