Interpolator based clock and data recovery (cdr) circuit with digitally programmable bw and tracking capability

Abstract

The present invention facilitates clock and data recovery () for serial data streams () by providing a mechanism that can be employed to maintain a fixed tracking capability of an interpolator based CDR circuit () at multiple data rates (e.g.,). The present invention further provides a wide data rate range CDR circuit (), yet uses an interpolator design optimized for a fixed frequency. The invention employs a rate programmable divider circuit () that operates over a wide range of clock and data rates (e.g.,) to provide various phase correction step sizes (e.g.,) at a fixed VCO clock frequency. The divider () and a finite state machine (FSM) () of the exemplary CDR circuit () are manually programmed based on the data rate (). Alternately, the data rate may be detected from a recovered serial data stream () during CDR operations (on-the-fly) utilizing a frequency detection circuit () to automatically program the divider () and FSM () to provide CDR circuit operation at the nearest base clock rate ().