The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 01, 2008
Filed:
Dec. 11, 2006
Jacques Miltat, Paris, FR;
Yoshinobu Nakatani, Tokyo, JP;
Jacques Miltat, Paris, FR;
Yoshinobu Nakatani, Tokyo, JP;
Infineon Technologies AG, Neubiberg, DE;
Altis Semiconductor SNC, Corbeil Essones Cedex, FR;
Centre National de la Recherche Scientifique (CNRS), Paris Cedex, FR;
Universite Paris-SUD, Orsay Cedex, FR;
Abstract
The present invention relates to a magnetoresistive hybrid memory cell comprising a first stacked structure comprising a magnetic tunnel junction including first and second magnetic regions stacked in a parallel, overlying relationship separated by a layer of non-magnetic material, wherein said first magnetic region being provided with a fixed first magnetic moment vector and said second magnetic region being provided with a free second magnetic moment vector which is free to be switched between the same and opposite directions with respect to said fixed first magnetic moment vector of said first magnetic region, a second stacked structure being at least partly arranged in a lateral relationship as to said first stacked structure and comprising a third magnetic region being provided with a fixed third magnetic moment vector and said second magnetic region; wherein said first and second structures being arranged in between at least two electrodes in electrical contact therewith. It further relates to a method of writing to and reading of a magnetoresistive hybrid memory cell, wherein a writing voltage pulse is applied to electrodes on both sides of only said second structure, and wherein a reading voltage pulse is applied to electrodes on both sides of only said first structure.