The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 25, 2007
Filed:
Oct. 12, 2004
Robert Paul Masleid, Monte Sereno, CA (US);
Steven T. Stoiber, Los Altos, CA (US);
Robert Paul Masleid, Monte Sereno, CA (US);
Steven T. Stoiber, Los Altos, CA (US);
Transmeta Corporation, Santa Clara, CA (US);
Abstract
A method and system for tiling a bias design for an integrated circuit device to facilitate efficient design rule checking. The method is implemented in a computer implemented design synthesis system. The method includes receiving a circuit netlist, wherein the circuit netlist represents an integrated circuit design to be realized in physical form. A deep N-well bias voltage distribution structure is provided within the circuit netlist, wherein the structure includes a plurality of tiles arranged to distribute a bias voltage to a plurality of N-wells of the circuit netlist.