The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 25, 2007
Filed:
Mar. 25, 2004
Masafumi Takahashi, Kanagawa, JP;
Kenji Ohmori, Kanagawa, JP;
Masafumi Takahashi, Kanagawa, JP;
Kenji Ohmori, Kanagawa, JP;
Kabushiki Kaisha Toshiba, Tokyo, JP;
Abstract
A logic circuit having a self-test function includes a plurality of F/Fs having at least first-, second- and last-stage scanning F/Fs, each having a clock input, a scanning input and a scanning output terminals. The scanning F/Fs are connected one another so as to supply a scanning clock signal to the clock input terminal of each scanning F/F and a signal from the scanning output terminal of the first-stage to the scanning input terminal of the second-stage for sequential logical operations. Also provided in the logic circuit are a data selector to select either an external scanning signal or a signal output from the scanning output terminal of the last-stage and fed back through a feed-back signal line and a scanning controller to supply a control signal to the data selector so as to supply the signal fed back from the last-stage to the scanning input terminal of the first-stage, thus controlling each F/F in an internal scanning mode. The signal from the last-stage is supplied from the logic circuit via an external scanning output terminal.