The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 25, 2007

Filed:

Apr. 28, 2005
Applicants:

Yasuhiro Tomita, Toyonaka, JP;

Hitoshi Suwa, Takatsuki, JP;

Manabu Komiya, Kyoto, JP;

Tamas Toth, Kefar Yona, IL;

Jeffrey Allan Jacob, Raanana, IL;

Avi Parvin, Netanya, IL;

Noam Eshel, Pardesia, IL;

Inventors:

Yasuhiro Tomita, Toyonaka, JP;

Hitoshi Suwa, Takatsuki, JP;

Manabu Komiya, Kyoto, JP;

Tamas Toth, Kefar Yona, IL;

Jeffrey Allan Jacob, Raanana, IL;

Avi Parvin, Netanya, IL;

Noam Eshel, Pardesia, IL;

Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

In conventional memory arrays in which a bit line is shared by memory cells, a cell current flows over into neighbor cell(s) in a program verify process, and therefore, the threshold of a memory cell to be programmed is erroneously determined to be lower. Therefore, in a program verify process, a control circuitwrites a fail value to a neighbor cell bufferwhen all neighbor cell(s) having an offset of n or less from a memory cell to be programmed are in the erased state, and when otherwise, writes a pass value to the neighbor cell buffer. The control circuitverifies input write data and also verifies data stored in the neighbor cell buffer(s). In the latter verify process, a verify voltage higher than an ordinary one is used to compensate for the leakage of cell current.


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