Memory device having open bit line architecture for improving repairability and method of repairing the same

Abstract

In a memory device having an open bit line architecture for improving repairability and a method of repairing the memory device, redundant memory cells used to repair defective cells are included even in first and second edge sub-arrays that are arranged at the edges of a memory array. Further, memory cells connected to some of the bit lines in a normal sub-array can be replaced with redundant memory cells included in the first edge sub-array, and memory cells connected to the remaining bit lines can be replaced with redundant memory cells included in the second edge sub-array. Therefore, in the memory device having an open bit line architecture according to the present invention, if all of the redundant memory cells included in normal sub-arrays have been exhausted through replacement, defective cells can be repaired using the redundant memory cells included in the edge sub-arrays. Therefore, the memory device and method of repairing the memory device according to the present invention are advantageous in that they can remarkably improve repairability.