The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 25, 2007
Filed:
Nov. 30, 2005
Ju Yeab Lee, Kyeongki-do, KR;
Ju Yeab Lee, Kyeongki-do, KR;
Hynix Semiconductor Inc., Kyoungki-do, KR;
Abstract
Non-volatile memory devices have a page buffer that can verify pre-erase. A non-volatile memory device may include a cell array having a plurality of strings consisting of memory cells disposed at the intersection regions of bit lines and word lines, and a plurality of page buffers connected to the bit lines through a sensing line. Each of the plurality of page buffers may include a pre-erase detection unit that detects pre-erase in response to a signal of the sensing line in order to verify whether data programmed into the memory cells have been erased, a main erase detection unit that detects main erase in response to a signal of the sensing line in order to verify whether data programmed into the memory cells have been erased, a latch circuit which stores data in response to an output signal of the pre-erase detection unit at the time of pre-erase verify and stores data in response to an output signal of the main erase detection unit at the time of main erase verify, and a verify unit that verifies pass or fail of the pre-erase or main erase in response to a signal of the latch circuit at the time of pre-erase verify or main erase verify.