The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 25, 2007
Filed:
May. 17, 2006
Mu-hsiang Huang, San Jose, CA (US);
Katsuya Nakashima, Isahaya, JP;
Yoshifumi Miyajima, Nagasaki, JP;
Masahiro Ichihashi, Nagasaki, JP;
Mu-Hsiang Huang, San Jose, CA (US);
Katsuya Nakashima, Isahaya, JP;
Yoshifumi Miyajima, Nagasaki, JP;
Masahiro Ichihashi, Nagasaki, JP;
Sony Corporation, Tokyo, JP;
Sony Electronics, Inc., Park Ridge, NJ (US);
Abstract
A method and apparatus are provided for a programmable impedance control circuit. In one example of the apparatus, a programmable impedance control circuit of an output driver of an input/output interface is provided. The programmable impedance control circuit includes a pull-up impedance programmed according to a multi-stage emulator and a pull-down impedance programmed according to the multi-stage emulator. The multi-stage emulator includes a first stage for calibrating a pull-up PMOS impedance at a voltage level Voh, a second stage for calibrating a pull-up NMOS impedance at a voltage level Vol, a third stage for calibrating a pull-down NMOS impedance at the voltage level Vol, a fourth stage for re-calibrating the pull-up NMOS impedance at the voltage level Vol, and fifth stage for calibrating a pull-down PMOS impedance at the voltage level Voh.