The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 25, 2007
Filed:
Jun. 08, 2006
Sunhom Paak, San Jose, CA (US);
Hsung Jai Im, Cupertino, CA (US);
Boon Yong Ang, Santa Clara, CA (US);
Jan L. DE Jong, Cupertino, CA (US);
Sunhom Paak, San Jose, CA (US);
Hsung Jai Im, Cupertino, CA (US);
Boon Yong Ang, Santa Clara, CA (US);
Jan L. de Jong, Cupertino, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
A test circuit for fabrication of transistors for Very Large Scale Integration ('VLSI') processing and method of use thereof are described. Transistors are formed in an array. A first decoder is coupled to gates of the transistors and configured to selectively pass voltage to the gates. A second decoder is coupled to drain regions of the transistors and configured to selectively pass voltage to the drain regions of the transistors. A third decoder is coupled to source regions of the transistors and configured to selectively pass voltage to the source regions of the transistors. A fourth decoder is coupled to body regions of the transistors and configured to selectively pass voltage to the body regions of the transistors.