The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 25, 2007

Filed:

Oct. 11, 2002
Applicants:

Rafael Antu, Antioch, CA (US);

Cathy Marie Drews, Morgan Hill, CA (US);

David A. Plomgren, San Carlos, CA (US);

Todd Edward Takken, Mt. Kisco, NY (US);

Inventors:

Rafael Antu, Antioch, CA (US);

Cathy Marie Drews, Morgan Hill, CA (US);

David A. Plomgren, San Carlos, CA (US);

Todd Edward Takken, Mt. Kisco, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/16 (2006.01); H01K 3/10 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method and apparatus that provides improved loop inductance of decoupling capacitors. Vias are moved close to the pads and close to each other. Instead of placing power and ground vias on opposite sides of the capacitor, these vias are moved around to the same side of the capacitor and are placed as close to each other as manufacturing tolerances will allow. For designs using standard two-terminal surface mount capacitors, two vias per capacitor, and standard manufacturing procedures (no vias inside pads, for example), the lowest possible loop inductance of the capacitor's connections to the printed circuit board planes is provided. This results in the lowest effective capacitor series input inductance.


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