The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 25, 2007
Filed:
Mar. 11, 2003
Jean-claude Six, Saint Contest, FR;
Jean-Claude Six, Saint Contest, FR;
NXP, B.V., Eindhoven, NL;
Abstract
The invention relates to a method for connecting a connecting surface of a first silicon wafer [WA] with a connecting surface of a second silicon wafer [WA] so as to form an insulated cavity after assembly, at least one of the two silicon wafers [WA] including at least one functional area [DA] intended to be within the cavity. The method according to the invention includes a step [PLTS] of depositing alloy soldering bumps [PLTC] on the connecting surface of the first silicon wafer [WA], said bumps [PLTC] being separated from one another by an even distance which is sufficiently small to cause joinings during the assembly of the two silicon wafers. Said step [PLTS] of depositing the soldering bumps [PLTE] is carried out during the step of depositing the soldering bumps [PLTE] intended for the electrical contacts. The method includes a reflux soldering step [RFX] for assembling the two silicon wafers by melting of the alloy soldering bumps. Application: Protection of semiconductor elements sensitive to the external conditions.