The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 18, 2007
Filed:
May. 04, 2006
Arthur A. Bright, Croton-on-Hudson, NY (US);
Paul G. Crumley, Yorktown Heights, NY (US);
Marc B. Dombrowa, Bronx, NY (US);
Steven M. Douskey, Rochester, MN (US);
Rudolf A. Haring, Cortlandt Manor, NY (US);
Steven F. Oakland, Colchester, VT (US);
Michael R. Ouellette, Westford, VT (US);
Scott A. Strissel, Byron, MN (US);
Arthur A. Bright, Croton-on-Hudson, NY (US);
Paul G. Crumley, Yorktown Heights, NY (US);
Marc B. Dombrowa, Bronx, NY (US);
Steven M. Douskey, Rochester, MN (US);
Rudolf A. Haring, Cortlandt Manor, NY (US);
Steven F. Oakland, Colchester, VT (US);
Michael R. Ouellette, Westford, VT (US);
Scott A. Strissel, Byron, MN (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.