Clock signal adjuster circuit

Abstract

The present invention relates to a clock signal distribution circuit for distributing the clock signal to circuits such as LSI integrated circuits, and, more specifically, provides a clock adjuster circuit, which performs phase difference adjustment of clock signals automatically. It is a circuit, which on driving a circuit element implemented on an LSI chip, supplies the clock signal, which is a reference for driving, is distributed subsequently from first distribution to lower-level distributions of a hierarchical structure, or from a fifth level distribution circuit '' to every area on the LSI chip, for example. At that time, delay of the clock signal is detected by a phase difference detector circuit, the delay data is automatically written to a delay adjuster circuit built into each of the fifth level distribution circuits ''. Using the delay data, the phase difference of the clock signals, is adjusted when the LSI chip is manufactured.