The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 11, 2007
Filed:
Aug. 11, 2005
Himanshu J. Verma, Mountain View, CA (US);
Paul T. Nguyen, Fremont, CA (US);
Paul A. Swartz, Hillsborough, CA (US);
Himanshu J. Verma, Mountain View, CA (US);
Paul T. Nguyen, Fremont, CA (US);
Paul A. Swartz, Hillsborough, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
A method and apparatus for the utilization of on-chip, programmable resources to implement a signal distortion characterization circuit. Programmable logic resources, such as programmable delay lines and phase shifting circuits, are utilized to sample the logic value of a test signal after the test signal has traversed a path under test (PUT). A counter is used to determine the number of logic high valued samples and the number of logic low valued samples during a test period. A ratio is then taken to determine the resulting duty cycle for the test period.