Delay-fault testing method, related system and circuit

Abstract

A testing approach involves selective application of clock signals to target circuitry. In an example embodiment (), a target circuit () having logic circuitry that processes data in response to an operational clock signal () having at least one clock period, is analyzed for delay faults. Test signals are applied to the logic circuitry while the logic circuitry is clocked with a high-speed test clock () having several clock-state transitions that occur during at least one clock period of the operational clock (). An output from the logic circuitry is analyzed for its state (e.g., as affected by delay in the circuitry). Delay faults are detected as a difference in state of the output of the logic circuitry. With this approach, circuits are tested using conventional testers () that operate at normal (e.g., slow) speeds while selectively clocking selected portions of the circuit at higher speeds for detecting speed-related faults therein.