The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 11, 2007
Filed:
Feb. 11, 2005
Dietmar Schmunkamp, Schoenaich, DE;
Andreas Wagner, Boeblingen, DE;
Tobias Webel, Schwaebisch-Gmuend, DE;
Ulrich Weiss, Holzgerlingen, DE;
Dietmar Schmunkamp, Schoenaich, DE;
Andreas Wagner, Boeblingen, DE;
Tobias Webel, Schwaebisch-Gmuend, DE;
Ulrich Weiss, Holzgerlingen, DE;
International Business Machines Corporation, Armonk, NY (US);
Abstract
The present invention relates to system clocking in computer systems. In particular, it relates to system clocking in high-end multi-processor, multi-node server computer systems with an enhanced degree of performance and reliability and to a method for dynamically switching between a first and a second clock signal, if the first should fail. More redundancy even to the Dynamic Clock Switching Circuit (DCSC) () and the wiring () from there to multiple, PLL-() free clock chips () is provided. Instead of only one DCSC () and one single wiring (), two of them (----) are used combined with a further particular logic present on each clock chip (), which in combination generate two synchronous, fine-tuned, minimum-shifted clock signals and select always the first of them to arrive at a FlipFlop controlling the output for clock distribution wiring.