The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 11, 2007
Filed:
Sep. 23, 2004
Robert C. Tufford, Chandler, AZ (US);
Jeffrey M. Harris, Chandler, AZ (US);
Douglas L. Sandy, Chandler, AZ (US);
Robert C. Tufford, Chandler, AZ (US);
Jeffrey M. Harris, Chandler, AZ (US);
Douglas L. Sandy, Chandler, AZ (US);
Motorola, Inc., Schaumburg, IL (US);
Abstract
A payload module () includes a payload subunit () coupled to the payload module, where the payload module has one of a 3U form factor, a 6U form factor and a 9U form factor. At least one multi-gigabit connector () is coupled to a rear edge () of the payload module and to the payload subunit, where the at least one multi-gigabit connector is coupled to communicatively interface the payload subunit to a backplane (), where the backplane includes a switched fabric () coincident with at least one of a VMEbus network and a PCI network, and where the switched fabric and at least one of the VMEbus network and the PCI network are communicatively coupled with the payload subunit through the at least one multi-gigabit connector. A payload module power connector () includes a plurality of pins (), where at least one of the plurality of pins has a length different from a remaining portion of the plurality of pins such that power between a main power bus () on the backplane and a payload module power bus () on the payload module is at least one of applied and removed, in a smooth and gradually ramped fashion over a time period (), where power and any concurrent data operations on the backplane remain uninterrupted and unaffected during the at least one of applying and removing power between the main power bus and the payload module power bus.