The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 11, 2007

Filed:

Nov. 29, 2005
Applicants:

Atsushi Yokoi, Kasugai, JP;

Masao Nakano, Kawasaki, JP;

Inventors:

Atsushi Yokoi, Kasugai, JP;

Masao Nakano, Kawasaki, JP;

Assignee:

Spansion LLC, Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); H01L 29/788 (2006.01); H01L 29/792 (2006.01);
U.S. Cl.
CPC ...
Abstract

On a channel region enclosed by a pair of diffusion layersA,B, a first insulating layer, a charge accumulative layer, and a second insulating layerare stacked up in this order, and on the second insulating layer, two control gate layersA,B spaced across a gap Gare disposed in the middle of the channel width direction. The charge accumulative layerhas discrete charge traps, and, accordingly, movement of charge in the layer is limited. In the charge accumulative layer, the charges injected depend on the writing voltage applied in control gate layersA,B and can be localized beneath the control gate layersA,B through which a writing voltage is applied. The presence or absence of charges can be controlled in every charge accumulative region beneath the control gate layersA,B, so that multi-value storage in the memory cell can be realized.


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