The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 11, 2007

Filed:

Oct. 17, 2005
Applicants:

Robert J. Chiu, Santa Clara, CA (US);

Jeffrey P. Patton, Santa Clara, CA (US);

Paul R. Besser, Sunnyvale, CA (US);

Minh Van Ngo, Fremont, CA (US);

Inventors:

Robert J. Chiu, Santa Clara, CA (US);

Jeffrey P. Patton, Santa Clara, CA (US);

Paul R. Besser, Sunnyvale, CA (US);

Minh Van Ngo, Fremont, CA (US);

Assignee:

Adavnced Micro Devices, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01);
U.S. Cl.
CPC ...
Abstract

A structure of an integrated circuit is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over a gate dielectric on the semiconductor substrate. Source/drain junctions are formed in the semiconductor substrate. Ultra-uniform suicides are formed on the source/drain junctions, and a dielectric layer is deposited above the semiconductor substrate. Contacts are then formed in the dielectric layer to the ultra-uniform silicides.


Find Patent Forward Citations

Loading…