The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 11, 2007
Filed:
Sep. 15, 2004
Shunpei Yamazaki, Setagaya, JP;
Osamu Nakamura, Atsugi, JP;
Masayuki Kajiwara, Atsugi, JP;
Junichi Koezuka, Atsugi, JP;
Koji Dairiki, Isehara, JP;
Toru Mitsuki, Atsugi, JP;
Toru Takayama, Atsugi, JP;
Hideto Ohnuma, Atsugi, JP;
Taketomi Asami, Kasukabe, JP;
Mitsuhiro Ichijo, Tochigi, JP;
Shunpei Yamazaki, Setagaya, JP;
Osamu Nakamura, Atsugi, JP;
Masayuki Kajiwara, Atsugi, JP;
Junichi Koezuka, Atsugi, JP;
Koji Dairiki, Isehara, JP;
Toru Mitsuki, Atsugi, JP;
Toru Takayama, Atsugi, JP;
Hideto Ohnuma, Atsugi, JP;
Taketomi Asami, Kasukabe, JP;
Mitsuhiro Ichijo, Tochigi, JP;
Semiconductor Energy Laboratory Co., Ltd., Kanagawa-ken, JP;
Abstract
It is intended to achieve the reduction in number of heat treatments carried out at high temperature (at least° C.) and the employment of lower temperature processes (° C. or lower), and to achieve step simplification and throughput improvement. In the present invention, a barrier layer (), a second semiconductor film (), and a third semiconductor layer () containing an impurity element (phosphorus) that imparts one conductive type are formed on a first semiconductor film () having a crystalline structure. Gettering is carried out in which the metal element contained in the first semiconductor film () is allowed to pass through the barrier layer () and the second semiconductor film () by a heat treatment to move into the third semiconductor film (). Afterward, the second and third semiconductor films () and () are removed with the barrier layer () used as an etching stopper.