The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 11, 2007

Filed:

Dec. 10, 2004
Applicants:

Daniel Reznik, Berlin, DE;

Mario Festag, Berlin, DE;

Inventors:

Daniel Reznik, Berlin, DE;

Mario Festag, Berlin, DE;

Assignee:

Finisar Corporation, Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01R 12/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

The invention relates to an electrical printed circuit board serving for electrical contact-connection of an integrated circuit. The printed circuit board has a dielectric forming the printed circuit board material; at least one ground inner layer connected to ground potential; and a supply voltage inner layer connected to the potential of the supply voltage. The invention further includes at least one locally formed inner layer electrically connected to the supply voltage inner layer; a first external terminal contact serving for electrical connection to a ground terminal of an integrated circuit; and a second external terminal contact serving for electrical connection to a supply voltage terminal of an integrated circuit. In addition, a first contact-connection is provided between the first external terminal contact and the at least one ground inner layer; and a second contact-connection is provided between the second external terminal contact and the at least one locally formed inner layer. The at least one locally formed inner layer and the at least one ground inner layer provide a printed circuit board decoupling capacitor for an integrated circuit.


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