The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 04, 2007
Filed:
Apr. 05, 2005
James F. Mcclellan, Gilbert, AZ (US);
Patrick G. Drennan, Gilbert, AZ (US);
Douglas A. Garrity, Gilbert, AZ (US);
David R. Locascio, Chandler, AZ (US);
Michael J. Mcgowan, Mesa, AZ (US);
James F. McClellan, Gilbert, AZ (US);
Patrick G. Drennan, Gilbert, AZ (US);
Douglas A. Garrity, Gilbert, AZ (US);
David R. LoCascio, Chandler, AZ (US);
Michael J. McGowan, Mesa, AZ (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
The present invention provides a method for tiling an integrated circuit having a critically matched device such as a transistor. The method obtains an advantage of automatically improving metallic density over critically matched devices thus yielding improved CMP. The method may include the steps of: identifying critically matched devices in the integrated circuit; placing metal tiles over the critically matched device; performing a density test around each critically matched device; and if a density test is not satisfied around a critically matched device, placing at least one metal strip over a critically matched device.