The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 04, 2007
Filed:
Feb. 11, 2005
Michael Stephen Floyd, Austin, TX (US);
Joshua David Friedrich, Austin, TX (US);
Elspeth Anne Huston, Poughkeepsie, NY (US);
Wolfgang Roesner, Austin, TX (US);
Rick John Weiss, Austin, TX (US);
Michael Stephen Floyd, Austin, TX (US);
Joshua David Friedrich, Austin, TX (US);
Elspeth Anne Huston, Poughkeepsie, NY (US);
Wolfgang Roesner, Austin, TX (US);
Rick John Weiss, Austin, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method, an apparatus and computer instructions are provided for specifying multiple voltage domains of a signal and macros in a processor chip and validating physical implementation and interconnections of the signal and macros. A set of attributes is provided for designs to define multiple voltage domains of a signal and macros in a processor chip. A first validation mechanism is then provided to validate that no electrical or logical errors created by logical connections between macros as defined by the set of attributes. A translation mechanism is provided to translate logical voltage description to a physical netlist for designers to connect powers to macros and signals. A second validation mechanism is provided to validate physical implementation adhere to designers' intent according to the set of attributes defined in the logical design.