The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 04, 2007

Filed:

Jun. 22, 2005
Applicants:

Richard D. J. Duce, San Jose, CA (US);

Himanshu J. Verma, Mountain View, CA (US);

Inventors:

Richard D. J. Duce, San Jose, CA (US);

Himanshu J. Verma, Mountain View, CA (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01);
U.S. Cl.
CPC ...
Abstract

Testing signal propagation delay of a shift register circuit is described. A ring oscillator has a first sequential element, a second sequential element, and a shift register circuit. The shift register circuit is coupled in series between the first sequential element and the second sequential element. The shift register circuit includes the at least one shift register and combinational logic coupled to the at least one shift register. The at least one shift register is configured to store a test data pattern of alternating logic ones and zeros. The combinational logic is coupled to receive a data signal from the first sequential element of the ring oscillator and coupled to receive a shift output signal from the at least one shift register. The combinational logic is configured to provide an exclusive logic function.


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