The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 04, 2007

Filed:

Jul. 29, 2004
Applicants:

Akihiro Furuta, Kawasaki, JP;

Nobuo Higaki, Kobe, JP;

Tetsuya Tanaka, Kyoto, JP;

Tsuneyuki Suzuki, Takatsuki, JP;

Inventors:

Akihiro Furuta, Kawasaki, JP;

Nobuo Higaki, Kobe, JP;

Tetsuya Tanaka, Kyoto, JP;

Tsuneyuki Suzuki, Takatsuki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/28 (2006.01); G06F 13/36 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention provides a DMA transfer controller includes: a transfer parameter storing unit for storing a bus occupation time value and transfer parameters of one set or a plurality of sets of DMA transfers for each of a plurality of logical processors; a data transfer performing unit for performing the DMA transfer on the basis of the DMA transfer parameters; a control unit for controlling the receive and transmit of the DMA transfer parameters and the start and the interruption of the DMA transfers; and a time measuring unit for starting to measure bus occupation elapse time when a first DMA transfer is started for each of the logical processors. When the bus occupation elapse time reaches the bus occupation time value, the control unit interrupts the DMA transfer that is currently performed to start the DMA transfers based on the transfer parameters related to the logical processors of a prescribed sequence.


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