The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 04, 2007

Filed:

Mar. 08, 2005
Applicants:

Ramnath Venkatraman, San Jose, CA (US);

Ruggero Castagnetti, Menlo Park, CA (US);

Joseph Eugene Glenn, Eden Prairie, MN (US);

Inventors:

Ramnath Venkatraman, San Jose, CA (US);

Ruggero Castagnetti, Menlo Park, CA (US);

Joseph Eugene Glenn, Eden Prairie, MN (US);

Assignee:

LSI Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 15/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Improved layouts of binary and ternary content addressable memory cells (BCAM and TCAM) are shown. A content addressable memory cell layout has a plurality of P+ diffusion areas and a plurality of N+ diffusion areas that do not enclose isolation regions and on which shallow trench isolation stress can exert minimal influence on the drive current of the memories. Further, all transistors in the content addressable memory cell layout are oriented in the same direction to avoid unintended variations in electrical performance. The CAM layouts are 'process friendly' to accommodate requirements of advanced process technologies such as the 90 nm process.


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