The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 27, 2007
Filed:
Nov. 21, 2005
Tassanee Payakapan, San Jose, CA (US);
Lee NI Chung, San Jose, CA (US);
Shahin Toutounchi, Pleasanton, CA (US);
Tassanee Payakapan, San Jose, CA (US);
Lee Ni Chung, San Jose, CA (US);
Shahin Toutounchi, Pleasanton, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
A Built-in Self Test (BIST) system is provided in a Field Programmable Gate Array (FPGA) that can adjust test signal patterns provided for testing after partial reconfiguration of the FPGA. The BIST system includes a decoder that monitors I/O signals and provides an output indicating when I/O signals change indicating partial reconfiguration has occurred. The decoder output is provided to a BIST test signal generator providing signals to an IP core of the FPGA as well as a BIST comparator for monitoring test results to change test signals depending on the partial configuration mode.