The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 27, 2007

Filed:

Mar. 29, 2004
Applicants:

Jerome J. Cartmell, Natick, MA (US);

Qun Fan, Boston, MA (US);

Steven T. Mcclure, Northboro, MA (US);

Robert Decrescenzo, Franklin, MA (US);

Haim Kopylovitz, Newton, MA (US);

Eli Shagam, Brookline, MA (US);

Inventors:

Jerome J. Cartmell, Natick, MA (US);

Qun Fan, Boston, MA (US);

Steven T. McClure, Northboro, MA (US);

Robert DeCrescenzo, Franklin, MA (US);

Haim Kopylovitz, Newton, MA (US);

Eli Shagam, Brookline, MA (US);

Assignee:

EMC Corporation, Hopkinton, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/16 (2006.01);
U.S. Cl.
CPC ...
Abstract

Handling a faulting memory of a pair of mirrored memories includes initially causing a non-faulting memory of the pair of mirrored memories to service all read and write operations for the pair of mirrored memories, determining that hardware corresponding to the faulting memory of the pair of mirrored memories has been successfully replaced to provide a new memory, in response to the new memory being provided, causing data to be copied from the non-faulting memory to the new memory while data is being read to and written from the non-faulting memory, and, in response to successful copying to the new memory, causing writes to be performed to both memories of the pair of mirrored memories and selecting one of the pair of mirrored memories for read operations when one or more read operations are performed. Handling a faulting memory may also include, in response to a write being performed to the non-faulting memory while data is being copied from the non-faulting memory to the new memory, causing the write to be performed to the non-faulting memory and the new memory.


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