The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 27, 2007

Filed:

May. 11, 2005
Applicants:

Massimiliano Frulio, Milan, IT;

Riccardo Riva Reggiori, Segrate, IT;

Andrea Sacco, Alessandria, IT;

Luca Figini, Lomazzo, IT;

Inventors:

Massimiliano Frulio, Milan, IT;

Riccardo Riva Reggiori, Segrate, IT;

Andrea Sacco, Alessandria, IT;

Luca Figini, Lomazzo, IT;

Assignee:

Atmel Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01); G11C 16/06 (2006.01);
U.S. Cl.
CPC ...
Abstract

A system and method for avoiding offset in and reducing the footprint of a non-volatile memory that has a plurality of memory bank circuits. Each memory bank circuit has memory cells coupled to sense amplifiers, row and column decoders coupled to the memory cells, and bias circuits coupled to the sense amplifiers. The system includes a reference cell matrix coupled to each of the plurality of memory bank circuits. The reference cell matrix is configured to provide reference cell current for each of the plurality of memory bank circuits.


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