The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 27, 2007
Filed:
May. 24, 2004
Sherif Hanna, Nashua, NH (US);
Greg J. Landry, Merrimack, NH (US);
Alan Refalo, Nashua, NH (US);
Jeyenth Vijayaraghavan, Nashua, NH (US);
Sherif Hanna, Nashua, NH (US);
Greg J. Landry, Merrimack, NH (US);
Alan ReFalo, Nashua, NH (US);
Jeyenth Vijayaraghavan, Nashua, NH (US);
Cypress Semiconductor Corporation, San Jose, CA (US);
Abstract
Disclosed are various embodiments of a differential logic to CMOS logic translator including a level-shifting and buffering stage configured to receive differential inputs and to provide resulting signals with lower common mode voltage. Further, a gain stage is included to receive the resulting signals and to provide increased swing signals. A CMOS buffer is also included and is configured to receive the increased swing signals and to provide a CMOS logic output. Also disclosed is a method of translating a differential logic signal to a CMOS logic signal including level-shifting and buffering differential input signals to provide resulting signals with lower common mode voltage. The method also includes using a gain stage to provide increased swing signals from the resulting lower common mode signals and using a CMOS buffer to provide a CMOS output from the increased swing signals.