The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 27, 2007

Filed:

Jun. 14, 2005
Applicants:

Shigeo Kouzuki, Kawasaki, JP;

Hideki Okumura, Hyogo, JP;

Wataru Saito, Kawasaki, JP;

Masaru Izumisawa, Kawasaki, JP;

Masahiko Shiomi, Yokohama, JP;

Hitoshi Kobayashi, Yokohama, JP;

Kenichi Tokano, Kawasaki, JP;

Satoshi Yanagisawa, Kawasaki, JP;

Hironori Yoshioka, Yokohama, JP;

Manabu Kimura, Yokohama, JP;

Inventors:

Shigeo Kouzuki, Kawasaki, JP;

Hideki Okumura, Hyogo, JP;

Wataru Saito, Kawasaki, JP;

Masaru Izumisawa, Kawasaki, JP;

Masahiko Shiomi, Yokohama, JP;

Hitoshi Kobayashi, Yokohama, JP;

Kenichi Tokano, Kawasaki, JP;

Satoshi Yanagisawa, Kawasaki, JP;

Hironori Yoshioka, Yokohama, JP;

Manabu Kimura, Yokohama, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor substrate of a first conduction type is provided for serving as a common drain to a plurality of power MISFET cells. A middle semiconductor layer is formed on the semiconductor substrate and has a lower impurity concentration than that of the semiconductor substrate. Pillar regions are formed on the middle semiconductor layer and include semiconductor regions of the first conduction type having a lower impurity concentration than that of the middle semiconductor layer.


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