The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 27, 2007
Filed:
Sep. 08, 2005
Johann Harter, Dresden, DE;
Wolfgang Mueller, Radebeul, DE;
Wolfgang Bergner, Dresden, DE;
Ulrike Grüning Von Schwerin, Munich, DE;
Till Schloesser, Dresden, DE;
Rolf Weis, Dresden, DE;
Johann Harter, Dresden, DE;
Wolfgang Mueller, Radebeul, DE;
Wolfgang Bergner, Dresden, DE;
Ulrike Grüning Von Schwerin, Munich, DE;
Till Schloesser, Dresden, DE;
Rolf Weis, Dresden, DE;
Infineon Technologies AG, Munich, DE;
Abstract
Stack and trench memory cells are provided in a DRAM memory cell array. The stack and trench memory cells are arranged so as to form identical cell pairs each having a trench capacitor, a stack capacitor and a semiconductor fin, in which the active areas of two select transistors for addressing the trench and stack capacitors are formed. The semiconductor fins are arranged in succession in the longitudinal direction to form cell rows and in this arrangement are spaced apart from one another by in each case a trench capacitor. Respectively adjacent cell rows are separated from one another by trench isolator structures and are offset with respect to one another by half the length of a cell pair. The semiconductor fins are crossed by at least two active word lines, which are orthogonal with respect to the cell rows, for addressing the select transistors realized in the semiconductor fin.