The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7299443 B1

PDF
Full Text
Expired
Date of Patent:
Nov. 20, 2007

Filed:

Dec. 19, 2005
Applicant:

Kenji Kumagai, Kawasaki, JP;

Inventor:

Kenji Kumagai, Kawasaki, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

First, an amount of a current flowing between a first wiring and a third wiring is estimated, and the number of stack vias required for connecting the first wiring and the third wiring is determined. Next, based on the number of stack vias, the number of virtual wirings for determining positions of the stack vias is determined. Thereafter, the virtual wirings are arranged in a forming region of the third wiring above the first wiring, for example, at an equal interval, and the stack vias are created in intersections of the first wiring and the virtual wirings. Thereafter, the virtual wirings are removed, and the third wiring is created. According to needs, a second wiring passing between the stack vias is created.


Find Patent Forward Citations

Kumagai, Kenji. (2007). Method for designing wiring connecting section and semiconductor device (U.S. Patent No. 7299443). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7299443

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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