The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 20, 2007
Filed:
May. 24, 2005
Victor Z. Slonim, Broomfield, CO (US);
Salim Abid, Lafayette, CO (US);
Victor Z. Slonim, Broomfield, CO (US);
Salim Abid, Lafayette, CO (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
A method of input/output (I/O) assignment for a circuit design for a programmable logic device (PLD) can include determining I/O types for I/O objects specified by the circuit design, defining a plurality of virtual I/O bank-groups, wherein each virtual I/O bank-group includes at least one virtual I/O bank, and binding I/O objects of the circuit design into I/O groups according to the I/O types. A binary compatibility matrix can be created. The binary compatibility matrix can indicate the compatibility between the virtual I/O bank-groups and the I/O groups based upon the I/O types of I/O objects within each I/O group. A determination can be made as to whether a feasible solution exists for I/O assignment of the I/O objects of the circuit design according to a plurality of constraints and the binary compatibility matrix.