The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 20, 2007

Filed:

Mar. 16, 2005
Applicants:

Roman Malendevich, Oceanside, CA (US);

Myles Sussman, San Mateo, CA (US);

Lawrence C. Gunn Iii, Encinitas, CA (US);

Inventors:

Roman Malendevich, Oceanside, CA (US);

Myles Sussman, San Mateo, CA (US);

Lawrence C. Gunn III, Encinitas, CA (US);

Assignee:

Luxtera, Inc., Carlsbad, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G02B 6/28 (2006.01); H01L 27/15 (2006.01);
U.S. Cl.
CPC ...
Abstract

This application describes, among others, wafer designs, testing systems and techniques for wafer-level optical testing by coupling probe light to/from the top of a wafer. A wafer level test system uses optical and electronic probes to search for and align with an optoelectronic alignment structure. The test system uses a located optoelectronic alignment structure as a reference point to locate other devices on the wafer. The system tests the operation of selected devices disposed on the wafer. The optoelectronic alignment loop is also used as an alignment reference of known performance for an adjacent device of unknown performance.


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