The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 20, 2007
Filed:
Jun. 07, 2005
Subramani Kengeri, San Jose, CA (US);
Deepak Sabharwal, New Delhi, IN;
Prakash Bhatia, Fremont, CA (US);
Sanjiv Kainth, New Delhi, IN;
Subramani Kengeri, San Jose, CA (US);
Deepak Sabharwal, New Delhi, IN;
Prakash Bhatia, Fremont, CA (US);
Sanjiv Kainth, New Delhi, IN;
Virage Logic Corporation, Fremont, CA (US);
Abstract
A method and system for testing the individual memory cells of a volatile memory cell array (e.g., SRAM) for data retention faults are described. In one embodiment of the invention, adjacent memory cells connected by a pair of common bit-lines are written with opposite, or complementary, data, for example, logical '0' and logical '1'. Next, the two memory cells are subjected to a stress condition by pre-charging the common bit-lines connecting the two adjacent memory cells, and then simultaneously asserting the word-line of each memory cell. Finally, the data in each cell is read and compared with the data written to the cell prior to generating the stress condition.