The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 20, 2007
Filed:
Feb. 27, 2006
Morihito Hasegawa, Kasugai, JP;
Hidekiyo Ozawa, Kasugai, JP;
Shoji Tajiri, Kasugai, JP;
Toshihiko Kasai, Kasugai, JP;
Morihito Hasegawa, Kasugai, JP;
Hidekiyo Ozawa, Kasugai, JP;
Shoji Tajiri, Kasugai, JP;
Toshihiko Kasai, Kasugai, JP;
Fujitsu Limited, Kawasaki, JP;
Abstract
The invention provides a DC-DC converter capable of being started up in a state in which an input voltage is low and capable of being structured without increasing a circuit size. A back-gate voltage (Vsb) is outputted from a back-gate voltage generating circuit (VBGN), and is inputted to a back gate of a transistor (FET). During a period during which an output voltage (Vout) is lower than a reference voltage (e), an oscillation signal (OS) is inputted to a gate of the transistor (FET), and the back-gate voltage (Vsb) is set at a grounded voltage. Therefore, the transistor (FET) has a reference threshold voltage (Vto). On the other hand, during a period during which the output voltage (Vout) is higher than the reference voltage (e), a pulse signal (PS) is inputted to the gate of the transistor (FET), and the back-gate voltage (Vsb) is set at an output voltage of a charge pump portion (). Therefore, the transistor (FET) has a threshold voltage higher than the reference threshold voltage (Vto).