The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7295641 B1

PDF
Full Text
Expired
Date of Patent:
Nov. 13, 2007

Filed:

Nov. 26, 2003
Applicants:

Curt Wortman, Ottawa, CA;

Jean Luc Berube, Hull, CA;

Inventors:

Curt Wortman, Ottawa, CA;

Jean Luc Berube, Hull, CA;

Assignee:

Altera Corporation, San Jose, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 25/00 (2006.01); H04L 25/40 (2006.01);
U.S. Cl.
CPC ...
Abstract

The phase of a data signal relative to a reference clock signal is approximated relatively accurately using only relatively coarse increments of phase shift between trial version of a sampling clock signal (derived from the reference clock signal). Information about which amounts of progressively greater phase shift in the sampling clock signal cause loss of alignment between a training pattern and training data in the data signal can be used for such purposes as identifying the amount of phase of shift of the reference clock signal that will be best for use in sampling the data signal during normal (post-training) operation.


Find Patent Forward Citations

Wortman, Curt. (2007). Phase alignment circuitry and methods (U.S. Patent No. 7295641). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7295641

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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