Power saving by disabling cyclic bitline precharge

Abstract

A method and system of accessing memory cells within a dynamic hardware memory block operated with a bitline precharge circuit, in which differential read/write access operations are performed by activating complementary bitlines. A reduction in power dissipation is realized by determining whether a next access operation following a current access operation is a read or write access, and performing a precharge of the bitlines of the array only when a read operation follows the current access operation. A conventional precharge control signal is combined with an external control signal indicating if the next cycle is a read cycle. The combination of the two signals can be used, for example, as input to a simple AND gate to generate an effective precharge signal. The effective precharge signal permits precharging of bitlines only when those bitlines are used for read access in a respective next cycle.