The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 06, 2007
Filed:
Nov. 20, 2003
Peter Barbosa, Dättwil, CH;
Jürgen Steinke, Albbruck, DE;
Peter Steimer, Ehrendingen, CH;
Luc Meysenc, Le Fontanil, FR;
Thierry Meynard, L'Union, FR;
Peter Barbosa, Dättwil, CH;
Jürgen Steinke, Albbruck, DE;
Peter Steimer, Ehrendingen, CH;
Luc Meysenc, Le Fontanil, FR;
Thierry Meynard, L'Union, FR;
ABB Research Ltd., Zurich, CH;
Abstract
A converter circuit is specified for switching a large number of switching voltage levels, which has n first switching groups for each phase, with the n-th first switching group being formed by a first power semiconductor switch and a second power semiconductor switch, and with the first first switching group to the-th switching group each being formed by a first power semiconductor switch and a second power semiconductor switch and by a capacitor, which is connected to the first and second power semiconductor switches, with each of the n first switching groups being connected in series to the respectively adjacent first switching group, and with the first and the second power semiconductor switches in the first first switching group being connected to one another. In order to reduce the amount of electrical energy stored in the converter circuit, n≧1 and p second switching groups and p third switching groups are provided, which are each formed by a first power semiconductor switch and a second power semiconductor switch and by a capacitor which is connected to the first and second power semiconductor switches, where p≧1 and each of the p second switching groups is connected in series with the respectively adjacent second switching group, and each of the p third switching groups is connected in series with the respectively adjacent third switching group, and the first second switching group is connected to the first power semiconductor switch in the n-th first switching group, and the first third switching group is connected to the second power semiconductor switch in the n-th first switching group. Furthermore, the capacitor in the p-th second switching group is connected in series with the capacitor in the p-th third switching group.