The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7292072 B1

PDF
Full Text
Expired
Date of Patent:
Nov. 06, 2007

Filed:

Jul. 14, 2005
Applicant:

Janardhanan S. Ajit, Irvine, CA (US);

Inventor:

Janardhanan S. Ajit, Irvine, CA (US);

Assignee:

Broadcom Corporation, Irvine, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03B 1/00 (2006.01); G11C 5/14 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of providing bias voltages for input output connections on low voltage integrated circuits. As integrated circuit voltages drop generally so does the external voltages that those circuits can handle. By placing input and output devices, in series, external voltages can be divided between the devices thereby reducing junction voltages seen by internal devices. By using external voltages as part of a biasing scheme for integrated circuit devices, stress created by the differential between external voltages and internal voltages can be minimized. Additionally device wells can be biased so that they are at a potential that is dependant on the external voltages seen by the low voltage integrated circuit.


Find Patent Forward Citations

Ajit, Janardhanan. (2007). Sub-micron high input voltage tolerant input output (i/o) circuit (U.S. Patent No. 7292072). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7292072

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