The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 06, 2007
Filed:
Jul. 24, 2003
Austin H. Lesea, Los Gatos, CA (US);
Peter H. Alfke, Los Altos, CA (US);
Austin H. Lesea, Los Gatos, CA (US);
Peter H. Alfke, Los Altos, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
In an integrated circuit, a layer including a plurality of conductive wires is described. A first wire, having sidewalls, is tapered from a proximal end which has a first width to a distal end which has a second width, to reduce width from the first width to the second width, and the first wire also has a substantially vertical surface. A second wire, spaced apart from the first wire, also has a substantially vertical surface. The first wire and the second wire are each horizontally disposed along side each other forming a part of a sidewall capacitor between facing sidewalls. Capacitors are created between the first substantially vertical surface and the second substantially vertical surface, the capacitors are respectively associated with capacitances and with a plurality of loads, the plurality of loads is progressively reduced responsive to a progressive reduction of the capacitances as associated with the first wire taper.